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PARAMETER
SYMBOL
CONDITIONS AND NOTES
MIN
TYP
MAX
UNIT
I2C TIMING CHARACTERISTICS
SCL clock frequency
1/t SCL
Bus timeout disabled (Note 3)
0
1
MHz
Bus time-out period
t timeout
f OSC = 20MHz, T A = 25°C
29
30
31
ms
f OSC = 16MHz to 23MHz
600,000 / f OSC
s
STOP to START condition bus
free time
Repeated START condition
hold time
Repeated START condition set-up
time
STOP condition set-up time
SDA data hold time
t BUF
t HD:STA
t SU:STA
t SU:STOP
t HD:DAT
0.5
0.26
0.26
0.26
0
μs
μs
μs
μs
ns
SDA data valid acknowledge time
SDA data valid time
SDA data set-up time
SCL clock low period
SCL clock high period
SDA, SCL fall time
SDA, SCL rise time
SDA, SCL input suppression
filter period
t VD:ACK
t VD:DAT
t SU:DAT
t LOW
t HIGH
t f
t r
t SP
(Note 4)
(Note 5)
(Note 6) (Note 7)
(Note 8)
0.05
0.05
100
0.5
0.26
50
0.45
0.45
120
120
μs
μs
ns
μs
μs
ns
ns
ns
Note 1. Subject to thermal dissipation characteristics of the device.
Note 2. Guaranteed by design, and is not production tested.
Note 3. Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held low
for t timeout . Disable bus time-out via the fault enable register 0x03[6].
Note 4. t VD:ACK = SCL low to SDA (out) low acknowledge time.
Note 5. t VD:DAT = minimum SDA output data valid time following SCL low transition.
Note 6. A master device must internally provide an SDA hold time of at least 300ns to ensure an SCL low state.
Note 7. The maximum SDA and SCL rise times are 300ns. The maximum SDA fall time is 250ns. This allows series protection resistors to be
connected between SDA and SCL inputs and the SDA/SCL bus lines without exceeding the maximum allowable rise time.
Note 8. Input filters on SDA, SCL, and ADDR suppress noise less than 50ns.
10
Atmel LED Driver-MSL3085
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